PPC440EP-3JC533C Applied Micro Circuits Corporation, PPC440EP-3JC533C Datasheet - Page 52

• Manufacturer Part Number: PPC440EP-3JC533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3JC533C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Lead Free Status / RoHS Status: Compliant

Table 8. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
52
PCI Interface
PCIAD00:31
PCIC0:3/BE0:3
PCIClk
PCIDevSel
PCIFrame
PCIGnt0/Req
PCIGnt1:5
PCIIDSel
PCIINT
PCIIRDY
PCIPar
PCIPErr
PCIReq0/Gnt
PCIReq1:5
PCIReset
PCISErr
PCIStop
PCITRDY
Revision 1.29 – May 07, 2008
Signal Name
Data Sheet
Address/Data bus (bidirectional).
PCI Command/Byte Enables
Provides timing to the PCI interface for PCI transactions.
Indicates the driving device has decoded its address as the target
of the current access.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Driven by the current master to indicate beginning and duration of
an access.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When the
internal arbiter is disabled, output is Req.
Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled.
Used as a chip select during configuration read and write
transactions.
Level sensitive PCI interrupt.
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Even parity.
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates to the PCI arbiter that the specified agent wishes to use
the bus. When the internal arbiter is enabled, input is PCIReq0.
When internal arbiter is disabled, input is Gnt.
An indication to the PCI arbiter that the specified agent wishes to
use the bus. Used only when internal PCI arbiter enabled.
Brings PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Current target is requesting the master to stop the current
transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
T
transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
arget agent’s ability to complete the current data phase of the
Description
.
440EP – PPC440EP Embedded Processor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
AMCC Proprietary
Notes
5
4
4