PPC440EP-3JC533C Applied Micro Circuits Corporation, PPC440EP-3JC533C Datasheet - Page 14

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PPC440EP-3JC533C

Manufacturer Part Number
PPC440EP-3JC533C
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of PPC440EP-3JC533C

Family Name
440EP
Device Core
PowerPC
Device Core Size
16b
Frequency (max)
533MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5/2.5V
Operating Supply Voltage (max)
1.6/2.7V
Operating Supply Voltage (min)
1.4/2.3V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
456
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PPC440EP-3JC533C
Manufacturer:
FSC
Quantity:
21 400
Part Number:
PPC440EP-3JC533C
Manufacturer:
AMCC
Quantity:
218
DMA to PLB4 Controller
This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB.
Features include:
Serial Ports (UART)
Features include:
IIC Bus Interface
Features include:
14
Revision 1.29 – May 07, 2008
• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2
• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
• Scatter/gather capability
• 128-byte buffer with programmable thresholds
• Up to four ports in the following combinations:
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA function on PLB 64
• Two IIC interfaces provided
• Support for Philips® Semiconductors I
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Includes an integrated boot-strap controller (BSC) that is multiplexed with the IIC0 interface
– One 8-pin
– Two 4-pin
– One 4-pin and two 2-pin
– Four 2-pin
Data Sheet
2
C Specification, dated 1995
440EP – PPC440EP Embedded Processor
AMCC Proprietary

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