ppc440ep Applied Micro Circuits Corporation (AMCC), ppc440ep Datasheet

ppc440ep

Manufacturer Part Number

ppc440ep

Description

Powerpc 440ep Embedded Processor

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.PPC440EP.pdf (87 pages)

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Features

Description

Designed specifically to address high-end embedded

applications, the PowerPC 440EP (PPC440EP)

provides a high-performance, low- power solution that

interfaces to a wide range of peripherals and

incorporates on-chip power management features.

This chip contains a high-performance RISC

processor, a floating point unit, DDR SDRAM

controller, PCI bus interface, control for external ROM

and peripherals, DMA with scatter-gather support,

Ethernet ports, serial ports, IIC interfaces, SPI

interface, USB ports, NAND Flash interface, and

general purpose I/O.

AMCC Proprietary

440EP

PowerPC 440EP Embedded Processor

• PowerPC

• Selectable processor:bus clock ratios of N:1, N:2.

• Floating Point Unit with single- and double-

• Dual bridged Processor Local Buses (PLBs) with

• Double Data Rate (DDR) Synchronous DRAM

• DMA support for external peripherals, internal

• PCI V2.2 interface (3.3V only). Thirty-two bits at

• Programmable interrupt controller supports

• Programmable General Purpose Timers (GPT).

667MHz with 32KB I-cache and D-cache with

parity checking.

precision and single-cycle throughput.

64- and 128-bit widths.

(SDRAM) interface operating up to 133MHz with

ECC.

UART and memory.

up to 66MHz.

interrupts from a variety of sources.

440 processor core operating up to

Technology: CMOS Cu-11, 0.13μm.

Package: 35mm, 456-ball standard plastic ball grid

array (E-PBGA), with and without lead (RoHS

compliant).

Typical power (measured): Less than 3W at 533MHz,

2.5W at 400MHz.

Supply voltages required: 3.3V, 2.5V, 1.5V.

• Two Ethernet 10/100Mbps half- or full-duplex

• Up to four serial ports (16550 compatible UART).

• Two USB ports. One USB 1.1 Host interface with

• External peripheral bus (16-bit data) for up to six

• Two IIC interfaces (one with boot parameter read

• NAND Flash interface.

• SPI interface.

• General Purpose I/O (GPIO) interface.

• JTAG interface for board level testing.

• Boot from PCI memory, NOR Flash on the

• Available in RoHS compliant lead-free package.

interfaces. Operational modes supported are MII,

RMII, and SMII with packet reject.

on-chip PHY. One USB 2.0 Device interface, with

dedicated DMA, configured as a 1.1 on-chip PHY

or a 2.0 UTMI.

devices with external mastering.

capability).

external peripheral bus, or NAND Flash on the

NAND Flash interface.

Revision 1.29 – May 07, 2008

Data Sheet

Part Number 440EP

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