PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet - Page 84

• Manufacturer Part Number: PPC440EPX-SUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-SUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Compliant

440EPx – PPC440EPx Embedded Processor
insertion buffer.
When using unbuffered DIMMS, the loading on the address bus will be considerably greater than the clock (up to
18 loads for double-sided DIMMs). In this case, it is strongly suggested that a delay of 500ps in the clock path so
that the Address/Command setup time at the DIMMs can be met. This delay is sufficient to meet the setup time,
without having to change the programmable delay (internal to the PPC440EPx) between the DQS/DQ/DM and the
clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500ps
later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for T
(± 0.25 cycle, or 1.5ns at 166MHz). In the case where it is not possible to anticipate which kind of DIMMs may be
employed in a system, it is always safe to use this 500ps clock delay, since registered DIMMs (the least heavily
loaded) will have more than enough margin (almost 1/2 cycle) to accommodate the slight decrease in address hold
time.
Termination Model
Figure 9. DDR SDRAM Simulation Signal Termination Model
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
84
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
PPC440EPx
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
MemClkOut
MemClkOut
10pF
10pF
V
Revision 1.30 – February 27, 2009
120Ω
TT
50Ω
30pF
= SOV
DD
/2
Data Sheet
AMCC Proprietary
DQSS