PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet - Page 59

• Manufacturer Part Number: PPC440EPX-SUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-SUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Compliant

Revision 1.30 – February 27, 2009
Table 8. Signal Functional Description (Sheet 4 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
External Slave Peripheral Interface
DMAAck0:3
DMAReq0
DMAReq1
DMAReq2:3
EOT0:3/TC0:3
PerAddr02:07
PerAddr08:31
PerData00:31
PerDataPar0:3
PerBLast
PerCS0
PerCS1:5
PerOE
PerReady
PerR/W
PerWBE0:3
PerErr
Data Sheet
Signal Name
End Of Transfer/Terminal Count.
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC440EPx to indicate that data transfers have
occurred.
Used by slave peripherals to indicate they are prepared to
transfer data.
Used by slave peripherals to indicate they are prepared to
transfer data.
Used by slave peripherals to indicate they are prepared to
transfer data.
Peripheral address bus used by the PPC440EPx when not in
external master mode; otherwise, used by external master.
Peripheral address bus used by the PPC440EPx when not in
external master mode; otherwise, used by external master.
Peripheral data bus used by the PPC440EPx when not in
external master mode; otherwise, used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
Peripheral data bus parity used by the PPC440EPx when not in
external master mode; otherwise, used by external master.
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
External peripheral device select.
External peripheral device select.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440EPx is the
bus master, it enables the selected device to drive the bus.
Used by the PPC440EPx when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it is used by the external master as an input to
indicate the direction of transfer.
External peripheral data bus byte enables.
External Error. Used as an input to record external slave
peripheral errors.
DD
(EOV
Description
DD
DD
for Ethernet)
440EPx – PPC440EPx Embedded Processor
(EOV
DD
for Ethernet)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Type
Notes
1, 5
1, 2
1, 4
1, 2
1, 2
1, 2
1, 2
1
1
1
1
2
1
1
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