MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 72

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

1
2
Chapter 5 Resets, Interrupts, and General System Control
5.8.4
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 must be written during the user reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
70
Bit 4 is reserved; writes will change the value but will have no effect on this MCU.
u = unaffected
Reset:
BKGDPE
STOPE
RSTPE
POR:
COPE
COPT
LVD:
Field
7
6
5
1
0
W
R
COPE
System Options Register 1 (SOPT1)
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA4/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA4/ACMPO/BKGD/MS pin functions as PTA4 or ACMPO.
1 PTA4/ACMPO/BKGD/MS pin functions as BKGD/MS.
RESET Pin Enable — This write-once bit when set enables the PTA5/IRQ/TCLK/RESET pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its
input-only port function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on
RESET.
0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ, or TCLK.
1 PTA5/IRQ/TCLK/RESET pin functions as RESET.
1
1
1
7
= Unimplemented or Reserved
COPT
1
1
1
6
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-6. SOPT1 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
STOPE
0
0
0
5
4
1
1
1
1
Description
3
0
0
0
0
0
0
0
0
2
BKGDPE
Freescale Semiconductor
1
1
1
1
RSTPE
u
(2)
0
0
0