MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 169

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

11.4.1.4
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
11.4.1.5
As shown in
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
11.4.1.7
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
Freescale Semiconductor
Figure
STOP Signal
Repeated START Signal
Arbitration Procedure
Clock Synchronization
11-8, a repeated START signal is a START signal generated without first generating
Figure
11-8).
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure
Inter-Integrated Circuit (S08IICV1)
11-9). When all
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