MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 151

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

10.3.3
10.3.4
Freescale Semiconductor
CLKST
FTRIM
Field
TRIM
Field
7:0
3:2
1
0
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
11
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.10FLL Bypassed, External reference clock is selected.
Reserved.
U
1
7
7
0
0
0
Table 10-4. ICS Status and Control Register Field Descriptions
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-3. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 10-5. ICS Trim Register (ICSTRM)
U
0
0
0
0
5
5
U
0
0
0
0
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
Internal Clock Source (S08ICSV1)
OSCINIT
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0
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