LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 60

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-10
Register: 0x04
Status
Read Only
Register Bank 0 or 1
This register contains important flags that indicate certain events have
occurred. Bits [7:3] are latched until the interrupt register is read, and are
reset by a hard reset, but not by a SCSI reset. The phase bits are not
normally latched. They may be latched (for stacked commands) by
setting
INT
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
INT
7
0
Configuration 2 (Config
GE
6
0
disconnected state. A command from either the target
group or the initiator group causes an Illegal Command
interrupt. An Enable Selection/Reselection command by
itself does not change modes. However, if another SCSI
device then selects the FSC, it is in the target state; if
another device reselects the FSC, it is then in the initiator
state. Similarly, any select command places the FSC in
Initiator mode, while the Reselect Sequence command
places the FSC in Target mode.
6
0
0
0
1
Interrupt
This bit is set whenever the FSC drives the INT/ output
true. It may be polled. It is buffered from the actual output
so that in wired-OR (shared interrupt) designs, this bit
indicates whether the FSC is attempting to interrupt the
microprocessor. Hardware reset, the Reset command, or
a read from the Interrupt register releases an active INT/
signal and also clears this bit.
5
0
0
1
0
Bits
PE
5
0
4
0
1
0
0
TC
4
0
2), bit 6.
Default
Command Mode
Miscellaneous
Initiator
Target
Disconnected State
VOC
3
0
MSG
2
x
C/D
1
x
I/O
0
x
7