LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 47

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3.1
Name
WR/
INT/
DREQ
DACK/
CLK
RESET
Microprocessor and DMA Interface Signals (Cont.)
Bump
45
42
2
3
48
44
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Type
I
O
O
I
I
I
Description
Active LOW register write signal. This TTL-
compatible input causes the FSC to write data into its
internal registers when CS/ is also true.
Active LOW, open drain interrupt signal to the
microprocessor. It is asserted on the rising edge of
CLK. It may be cleared by reading the interrupt
register, by a host hardware reset, or the Reset
command (but not by a SCSI reset). This output
cannot be masked by the user. An external pull-up is
required. See
3-state, active HIGH DMA request signal to the DMA
controller. DREQ remains true as long as the FIFO
either:
If Threshold Eight mode is enabled, DREQ is not
asserted until the FIFO can accommodate an
eight-byte transfer. When the TESTIN/ pin is enabled,
DREQ is the output of the “AND” tree (see the
TESTIN/ pin description on
Active LOW DMA acknowledge from the DMA
controller. DACK/ accesses the FIFO only, while CS/
accesses any register, including the FIFO.
Square wave clock input that generates internal chip
timing. The maximum frequency is 40 MHz. The
minimum frequency for asynchronous SCSI is
10 MHz. The minimum frequency for synchronous
SCSI is 12 MHz. The synchronous transmission
period is equal to the CLK period multiplied by the
value in the synchronous transfer period register. The
asynchronous transmission rate is indirectly affected
by the CLK period.
Active HIGH chip reset. Reset must be asserted for
at least two CLK periods after the voltage on the
power pins has reached minimum VDD.
contains at least one byte to send to memory
DMA read,
has room for one more byte during DMA write.
Figure B.1
for details.
page
3-5).
3-3