LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 136
LSI53CF92A-64QFP
Manufacturer Part Number
LSI53CF92A-64QFP
Description
Manufacturer
LSI
Datasheet
1.LSI53CF92A-64QFP.pdf
(158 pages)
Specifications of LSI53CF92A-64QFP
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Table 6.16
1. Assertion pending. If the FIFO is empty during DMA read, or full during DMA write, then assertion
2. Single DMA transfer only.
3. Multiple DMA transfers only.
6-20
Symbol
is not pending.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
Parameter
DACK/ HIGH to DREQ HIGH
DACK/ LOW to DREQ LOW
DACK/ HIGH to DACK/ LOW
DBRD/ HIGH to DREQ LOW
DACK/ LOW to DBRD/ LOW
DBRD/ pulse width
DBRD/ HIGH to DBRD/ LOW
DBRD/ LOW to data valid
DBRD/ HIGH to data bus disable
DBRD/ LOW to DBRD/ LOW
DBRD/ HIGH to DBRD/ HIGH
DBRD/ HIGH to DACK/ HIGH
DBWR/ HIGH to DREQ LOW
DACK/ LOW to DBWR/ LOW
DBWR/ pulse width
DBWR/ HIGH to DBWR/ LOW
Data setup to DBWR/ HIGH
Data hold from DBWR/ HIGH
DBWR/ LOW to DBWR/ LOW
DBWR/ HIGH to DBWR/ HIGH
DBWR/ HIGH to DACK/ HIGH
Burst Mode DMA Interface (Multiplexed Mode)
Table 6.16
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the Burst Mode DMA Interface, Multiplexed Mode.
t
t
t
t
t
CP
CP
CP
3 t
3 t
CP
CP
3 t
3 t
Min
30
10
–
–
0
–
–
0
–
0
4
0
CP
CP
CP
CP
+5
+5
+5
+5
+5
2 t
2 t
CP
CP
Max
+ t
+ t
30
30
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CL
CL
+30
+30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
2
3
3
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