LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 22

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.1 Typical SCSI Operation
2-2
The LSI53CF92A is the newest member of the LSI53C90 family, with
additional features such as Fast SCSI transfer rates, single-pin SE SCSI,
8-bit DMA mode, and TolerANT Active Negation Technology.
In target mode, the microprocessor enables selection and then waits for
an interrupt. Eventually an initiator selects the FSC. It then automatically
steps through the selection and command phases before generating an
interrupt. When the interrupt occurs, the entire CDB is in the FIFO along
with any message bytes sent by the initiator.
After the selection phase has been successfully completed, the FSC may
transfer bytes in any SCSI information phase whether it is operating in
initiator or target mode. The FSC supports disconnect/reselect in both
initiator and target modes, making high performance multithreaded
systems easy to implement.
The FSC may transfer data phase bytes across the bus synchronously, at
speeds up to 10 Mbytes/s, or asynchronously, at speeds up to 5 Mbytes/s.
Refer to
information. The difference between asynchronous and synchronous
operation is transparent to the user except that the synchronous offset
and the synchronous transfer period registers must be programmed prior
to synchronous data transfer. The default, after hardware or software
reset, is asynchronous transmission.
Data phase bytes are usually transferred using DMA. The
microprocessor programs an external DMA controller, programs the FSC
transfer count register, issues one of several FSC data transfer
commands, then waits for an interrupt. The DMA controller and the FSC
transfer all the data without microprocessor intervention.
To end the SCSI transaction, the FSC target places a status byte and a
message byte in the FIFO. It then issues one of two single commands
which causes the FSC first to assert Status phase, send the first byte,
assert Message In phase, send the second byte, disconnect from the
SCSI bus (after the initiator releases ACK/ [Acknowledge]) and interrupt
the microprocessor.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Section 2.6, “SCSI Data Transfer Rates,”
on
page
2-14, for more