LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 36

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.7.2 Soft Reset
2-16
A soft reset is applied when the SCSI Bus reset condition is received
through the RST/ pin, or when the Reset SCSI Bus command is issued,
which asserts the RST/ pin. This condition resets the following subset of
the functions reset by the hard reset:
The Reset SCSI Bus command causes the RST/ signal to be asserted.
See
A SCSI Bus reset may occur in any mode. The RST/ signal is asserted
by another SCSI device on the bus, and returns the chip to a
disconnected state. The chip generates a SCSI Reset interrupt to the
microprocessor if the interrupt is not disabled by bit 6 of the
Configuration 1 (Config 1)
when the microprocessor clears the interrupt, a new interrupt is
generated. This new interrupt must be serviced.
The Reset SCSI Bus command asserts the SCSI RST/ pin for
approximately 25 s and returns the chip to disconnected status. A SCSI
reset interrupt is generated if the interrupt is not disabled by Bit 6 of the
Configuration 1 (Config 1)
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Resets DMA interface
Resets bus-initiated selection/reselection module
Resets command sequence module
Resets Sequence Step and clears Sequencer Mode bits
(Enable Select/Reselect = 0, Target = 0, Initiator = 0)
Initializes Command register FIFO to empty
Releases all SCSI signals except RST/
Resets disconnect, initiator, and target command modules
Chapter 5, “Command Set,”
register. If the SCSI bus reset is still active
register.
for further description of this command.