PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 82
PSD813F2-A-70J
Manufacturer Part Number
PSD813F2-A-70J
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2-A-70J.pdf
(128 pages)
Specifications of PSD813F2-A-70J
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
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Power management
17.4
Table 31.
82/128
Bit 0
Bit 1
Bit 2
Bit 3
Bit
X
APD Enable
X
PLD Turbo
Name
Figure 32. Enable Power-down flowchart
PLD power management
The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70ns. The propagation
delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs
change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0'
(turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC
power, AC power, and propagation delay.
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
Power Management mode registers PMMR0
0
0 =
off
1 =
on
0
0 =
on
1 =
off
Not used, and should be set to zero.
Automatic Power-down (APD) is disabled.
Automatic Power-down (APD) is enabled.
Not used, and should be set to zero.
PLD Turbo mode is on
PLD Turbo mode is off, saving power.
Doc ID 7833 Rev 7
No
by setting PMMR0 bits 4 and 5
Disable desired inputs to PLD
and PMMR2 bits 2 through 6.
Set PMMR0 Bit 1 = 1
PSD in Power
OPTIONAL
for 15 CLKIN
Enable APD
ALE/AS idle
Down Mode
clocks?
RESET
Description
Yes
(1)
AI02892
PSD8XXFX
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