PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 75

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
16.19
16.20
Enable Out
The Enable Out register can be read by the MCU. It contains the output enable values for a
given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state
and the pin is in input mode.
Ports A and B – functionality and structure
Ports A and B have similar functionality and structure, as shown in
can be configured to perform one or more of the following functions:
●
●
●
●
●
●
●
●
●
Figure 27. Port A and port B structure
MCU I/O mode
CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B.
McellBC7-McellBC0 can be connected to port B or port C.
CPLD input – Via the input macrocells (IMC).
Latched Address output – Provide latched address output as per
Address In – Additional high address inputs using the input macrocells (IMC).
Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew
rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.
Data port – port A to D7-D0 for 8 bit non-multiplexed bus
Multiplexed Address/Data port for certain types of MCU bus interfaces.
Peripheral mode – port A only
ALE
ADDRESS
MACROCELL OUTPUTS
WR
WR
WR
ENABLE PRODUCT TERM ( .OE )
CONTROL REG.
CPLD - INPUT
DATA OUT
READ MUX
DIR REG.
D
D
G
D
D
REG.
P
D
B
Doc ID 7833 Rev 7
Q
Q
Q
Q
A [ 7:0 ] OR A [ 15:8 ]
ADDRESS
DATA OUT
DATA IN
OUTPUT
OUTPUT
SELECT
MUX
ENABLE OUT
MACROCELL
Figure
INPUT
Table
27. The two ports
22.
A OR B PIN
PORT
I/O ports
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