PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 46

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

Page register
13
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Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Figure 11
internal data bus D0-D7. The MCU can write to or read from the Page register. The Page
register can be accessed at address location CSIOP + E0h.
Figure 11. Page register
shows the Page register. The eight flip-flops in the register are connected to the
RESET
R/W
D 0 - D 7
Doc ID 7833 Rev 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
REGISTER
PAGE
Q 0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
CPLD
PLD
AND
INTERNAL
SELECTS
AND LOGIC
PSD8XXFX
AI02871B