LM93CIMTX National Semiconductor, LM93CIMTX Datasheet - Page 84
![](/photos/31/35/313579/56pin_tssop_sml.jpg)
LM93CIMTX
Manufacturer Part Number
LM93CIMTX
Description
Manufacturer
National Semiconductor
Datasheet
1.LM93CIMTX.pdf
(92 pages)
Specifications of LM93CIMTX
Operating Temperature (max)
85C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
TSSOP
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM93CIMTX
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
LM93CIMTX/NOPB
Manufacturer:
NSC
Quantity:
400
www.national.com
Register
Address
Register
Address
16.0 Registers
16.10 OTHER MASK REGISTERS
16.10.1 Register ECh GPI Error Mask
These bits mask the corresponding bits in the B_ and H_GPI Error Status Registers. They do not effect the GPI State register.
16.10.2 Register EDh Miscellaneous Error Mask
EDh
ECh
Read/
Write
Read/
R/W
Write
R/W
Bit
7:6
0
1
2
3
4
5
Bit
0
1
2
3
4
5
6
7
Miscellaneous
DVccp1_MSK
DVccp2_MSK
SCSI1_MSK
SCSI2_MSK
VRD1_MSK
VRD2_MSK
GPI Error
Error Mask
Register
Register
Name
Mask
Name
Name
(Continued)
RES
GPI0_MSK
GPI1_MSK
GPI2_MSK
GPI3_MSK
GPI4_MSK
GPI5_MSK
GPI6_MSK
GPI7_MSK
Name
_MSK
Bit 7
GPI7
Bit 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RES
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
_MSK
GPI6
Bit 6
Bit 6
When this bit is set, VRD1_HOT error events are masked.
When this bit is set, VRD2_HOT error events are masked.
When this bit is set, SCSI_TERM1 error events are masked.
When this bit is set, SCSI_TERM2 error events are masked.
When this bit is set, dynamic Vccp limit error events for
AD_IN7 (CPU1) are masked.
When this bit is set, dynamic Vccp limit error events for
AD_IN8 (CPU2) are masked.
Reserved
When this bit is set, GPI0 error events are masked.
When this bit is set, GPI1 error events are masked.
When this bit is set, GPI2 error events are masked.
When this bit is set, GPI3 error events are masked.
When this bit is set, GPI4 error events are masked.
When this bit is set, GPI5 error events are masked.
When this bit is set, GPI6 error events are masked.
When this bit is set, GPI7 error events are masked.
DVccp2
_MSK
_MSK
Bit 5
GPI5
Bit 5
84
_MSK
GPI4
DVccp1
Bit 4
_MSK
Bit 4
Description
Description
_MSK
Bit 3
GPI3
SCSI2
_MSK
Bit 3
_MSK
GPI2
Bit 2
SCSI1
_MSK
Bit 2
_MSK
Bit 1
GPI1
VRD2
_MSK
Bit 1
_MSK
Bit 0
GPI0
VRD1
_MSK
Bit 0
Default
Default
Value
Value
FFh
3Fh