LM93CIMTX National Semiconductor, LM93CIMTX Datasheet - Page 78
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LM93CIMTX
Manufacturer Part Number
LM93CIMTX
Description
Manufacturer
National Semiconductor
Datasheet
1.LM93CIMTX.pdf
(92 pages)
Specifications of LM93CIMTX
Operating Temperature (max)
85C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
TSSOP
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM93CIMTX
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
LM93CIMTX/NOPB
Manufacturer:
NSC
Quantity:
400
www.national.com
Register
Address
16.0 Registers
16.8.24 Register E2h LM93 Status Control
E2h
Read/
Write
R/W
Lock
X
LM93 Status/
Register
Control
Name
Bit
5:4
0
1
2
3
6
7
(Continued)
TACH_EDGE
HOST_ERR
BMC_ERR
GP15_AM
GPI4_AM
OVRID
Name
_ERR
Bit 7
BMC
ASF
TACH_EDGE
0h
1h
2h
3h
HOST
_ERR
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit 5
TACH_EDGE
If this bit is set, all PWM outputs go to 100% duty
cycle.
If this bit is set, BMC error registers support ASF, i.e.
reset on read. When not in ASF mode, a write “1” is
required to clear the bits in the BMC error status
registers.
GPI4 Auto Mask Enable
If this bit is set, an error event on GPI4 causes all
other error events to be masked.
The BMC Error Status registers do not reflect any
new error events until the GPI4_ERR bit is cleared in
the B_GPI Error Status register. The HOST Error
Status registers do not reflect any new error events
until the GPI4_ERR bit is cleared in the H_GPI Error
Status register.
If a CPU_THERMTRIP signal is connected to GPIO4,
this ensures that unwanted error events do not fire
once CPU_THERMTRIP is asserted.
GPI5 Auto Mask Enable
This bit works exactly the same as GPI4_AM, but
applies to GPI5.
This field determines what type of edges are used for
measuring fan tach pulses. This effects all four
tachometer inputs.
This bit gets set if any error bit is set in any of the
Host Error Status registers (H_).
This bit gets set if any error bit is set in any of the
BMC Error Status registers (B_). When this bit is set,
ALERT are asserted if enabled.
Either rising or falling edges may
be used.
Rising edges only
Falling edges only
Reserved
78
Tachometer Measurements
Bit 4
Edge Type Used for
GPI5_AM GPI4_AM
Bit 3
Description
Bit 2
Bit 1
ASF
OVRID
Bit 0
Default
Value
00h