LM93CIMTX National Semiconductor, LM93CIMTX Datasheet - Page 46
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LM93CIMTX
Manufacturer Part Number
LM93CIMTX
Description
Manufacturer
National Semiconductor
Datasheet
1.LM93CIMTX.pdf
(92 pages)
Specifications of LM93CIMTX
Operating Temperature (max)
85C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
TSSOP
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM93CIMTX
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
LM93CIMTX/NOPB
Manufacturer:
NSC
Quantity:
400
www.national.com
Register
Address
Bit
16.0 Registers
16.5.2 Register 49h H_Error Status 2
0
1
2
3
4
5
6
7
49h
AD1_ERR
AD2_ERR
AD3_ERR
AD4_ERR
AD5_ERR
AD6_ERR
AD7_ERR
AD8_ERR
Name
Read/
Write
RWC
Register
Status 2
H_Error
Name
RWC This bit is set when the AD_IN1 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN2 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN3 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN4 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN5 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN6 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN7 voltage has fallen outside the range defined
RWC This bit is set when the AD_IN8 voltage has fallen outside the range defined
R/W
(Continued)
by the AD_IN1 Low Limit and the AD_IN1 High Limit registers.
by the AD_IN2 Low Limit and the AD_IN2 High Limit registers.
by the AD_IN3 Low Limit and the AD_IN3 High Limit registers.
by the AD_IN4 Low Limit and the AD_IN4 High Limit registers.
by the AD_IN5 Low Limit and the AD_IN5 High Limit registers.
by the AD_IN6 Low Limit and the AD_IN6 High Limit registers.
by the AD_IN7 Low Limit and the AD_IN7 High Limit registers.
by the AD_IN8 Low Limit and the AD_IN8 High Limit registers.
ADIN8
_ERR
Bit 7
ADIN7
_ERR
Bit 6
ADIN6
_ERR
Bit 5
46
Description
ADIN5
_ERR
Bit 4
ADIN4
_ERR
Bit 3
ADIN3
_ERR
Bit 2
ADIN2
_ERR
Bit 1
ADIN1
_ERR
Bit 0
Masking
S3, S4/5
S3, S4/5
S3, S4/5
S3, S4/5
S3, S4/5
S3, S4/5
S3, S4/5
S3, S4/5
Sleep
Default
Value
00h