LM93CIMTX National Semiconductor, LM93CIMTX Datasheet - Page 63

• Manufacturer Part Number: LM93CIMTX
• Manufacturer: National Semiconductor

Specifications of LM93CIMTX

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Not Compliant

Register
Address
Register
Address
16.0 Registers
16.8.2 Register BDh Special Function Control 2 (Smart Tach Mode Enable and Fan Control Temperature Resolution
Control)
Application Note: Enabling Smart Tach mode is not supported while either PWM output is configured for 22.5 kHz. The behavior
of the part is undefined if this configuration is programmed. Register E0h Special Function TACH to PWM Binding must be setup
when Smart Tach modes are enabled.
16.8.3 Register BEh GPI/VID Level Control
See the DC Electrical Characteristics for exact V
BDh
BEh
Read/
Read/
Write
Write
R/W
R/W
3:2
Bit
0
1
4
5
6
7
Bit
0
1
2
3
4
5
6
7
P1_VID_LVL
P2_VID_LVL
Special Function
Level Control
GPI4_LVL
GPI5_LVL
GPI6_LVL
GPI7_LVL
Register
Name
GPI/VID
RES
Control 2
(Continued)
Register
Name
Name
ZN12_RS
ZN34_RS
Name
STE1
STE2
STE3
STE4
RES
RES
GPI7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
_LVL
R
Bit 7
RES
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
If set, P1_VIDx inputs use alternate lower V
If set, P2_VIDx inputs use alternate lower V
Reserved
If set, GPIO4 input use alternate lower V
If set, GPIO5 input use alternate lower V
If set, GPIO6 input use alternate lower V
If set, GPIO7 input use alternate lower V
IH
Bit 6
GPI6
_LVL
and V
Bit 6
RES
Enable Smart Tach for Tach 1
Enable Smart Tach for Tach 2
Enable Smart Tach for Tach 3
Enable Smart Tach for Tach 4
When this bit is set, the auto fan control will use
0.5˚C of resolution for zones 1 and 2
When this bit is set, the auto fan control will use
0.5˚C of resolution for zones 3 and 4
Reserved
Reserved
IL
Bit 5
GPI5
_LVL
levels.
ZN34
Bit 5
_RS
63
Bit 4
GPI4
_LVL
ZN12
Bit 4
_RS
Description
Description
Bit 3
STE4
Bit 3
RES
Bit 2
IH
IH
IH
IH
STE3
Bit 2
and V
and V
and V
and V
IH
IH
and V
and V
P2_VID
Bit 1
_LVL
IL
IL
IL
IL
STE2
levels
levels
levels
levels
Bit 1
IL
IL
levels
levels
P1_VID
Bit 0
_LVL
STE1
Bit 0
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Default
Default
Value
Value
00h
00h