ISP1160BM01TM STEricsson, ISP1160BM01TM Datasheet - Page 37

• Manufacturer Part Number: ISP1160BM01TM
• Manufacturer: STEricsson

Specifications of ISP1160BM01TM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
10. HC registers
Table 7:
9397 750 13963
Product data
Read
00
01
02
03
04
05
0D
0E
0F
11
Address (Hex)
Write
N/A
81
82
83
84
85
8D
N/A
N/A
91
HC registers summary
Register
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcFmInterval
HcFmRemaining
HcFmNumber
HcLSThreshold
Wake-up by pin CS_N (software wake-up):
external microprocessor issues a chip select signal through pin CS_N to the
ISP1160. This method of access to the ISP1160 internal registers is a software
wake-up.
Wake-up by USB devices:
root hub port issues a resume signal to the HC through the USB bus, switching the
HC from the USBSuspend state to the USBResume state. This will also set
bit ResumeDetected of the HcInterruptStatus register (03H to read, 83H to write).
No matter which method is used to wake up the HC from the USBSuspend state, the
corresponding interrupt bits must be enabled before the HC goes into the
USBSuspend state so that the microprocessor can receive the correct interrupt
request to wake up the HC.
The HC contains a set of on-chip control registers. These registers can be read or
written by the Host Controller Driver (HCD). The Control and Status register sets,
Frame Counter register sets, and Root Hub register sets are grouped under the
category of HC Operational registers (32 bits). These operational registers are made
compatible to OpenHCI (Host Controller Interface) operational registers. This allows
the OpenHCI HCD to be easily ported to the ISP1160.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD must not assume that a reserved field contains logic 0.
Furthermore, the HCD must always preserve the values of the reserved field. When a
R/W register is modified, the HCD must first read the register, modify the bits desired,
and then write the register with the reserved bits still containing the original value.
Alternatively, the HCD can maintain an in-memory copy of previously written values
that can be modified and then written to the HC register. When a ‘write to set’ or ‘clear
the register’ is performed, bits written to reserved fields must be logic 0.
As shown in
32-bit operational registers are similar to the offsets defined in the OHCI specification
with the addresses being equal to offset divided by 4.
Table
Rev. 05 — 24 December 2004
7, the addresses (the commands for reading registers) of these
Width Reference
32
32
32
32
32
32
32
32
32
32
Section 10.1.1 on page 37
Section 10.1.2 on page 38
Section 10.1.3 on page 39
Section 10.1.4 on page 40
Section 10.1.5 on page 42
Section 10.1.6 on page 43
Section 10.2.1 on page 44
Section 10.2.2 on page 45
Section 10.2.3 on page 46
Section 10.2.4 on page 47
For the USB bus resume, a USB device attached to the
During the USBSuspend state, an
Embedded USB Host Controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Functionality
HC control and status registers
HC frame counter registers
ISP1160
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