ISP1160BM01TM STEricsson, ISP1160BM01TM Datasheet - Page 16

• Manufacturer Part Number: ISP1160BM01TM
• Manufacturer: STEricsson

Specifications of ISP1160BM01TM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13963
Product data
Fig 13. HC interrupt logic.
HcInterruptEnable
HcInterruptStatus
register
register
RHSC
RHSC
FNO
FNO
MIE
UE
RD
SO
UE
RD
SO
SF
SF
There are two groups of interrupts represented by group 1 and group 2 in
A pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus
register). On occurrence of any of these events, the corresponding bit would be set to
logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,
the 6-input OR gate would output a logic 1. This output is AND-ed with the value of
MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in
the Hc PInterrupt register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The Hc PInterrupt and Hc PInterruptEnable registers work in the
same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt
group 2. The output from the 6-input OR gate is connected to a latch, which is
controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register).
In the event in which the software wishes to temporarily disable the interrupt output of
the ISP1160 Host Controller, the following procedure should be followed:
1. Make sure that the InterruptPinEnable bit in the HcHardwareConfiguration
2. Clear all bits in the Hc PInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
register is set to logic 1.
group 2
OR
Rev. 05 — 24 December 2004
INT
HcµPInterrupt
register
LATCH
OR
Embedded USB Host Controller
LE
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HcµPInterruptEnable
HcHardwareConfiguration
register
InterruptPinEnable
register
ISP1160
004aaa102
Figure
15 of 88
13.