ISP1160BM01TM STEricsson, ISP1160BM01TM Datasheet - Page 10

• Manufacturer Part Number: ISP1160BM01TM
• Manufacturer: STEricsson

Specifications of ISP1160BM01TM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Product data
8.2 DMA mode
The ISP1160 also provides the DMA mode for external microprocessors to access its
internal FIFO buffer RAM. Data can be transferred by the DMA operation between a
microprocessor’s system memory and the ISP1160’s internal FIFO buffer RAM.
Remark: The DMA operation must be controlled by the external microprocessor
system’s DMA controller (Master).
Figure 4
ISP1160. The ISP1160 provides a DMA channel controlled by DREQ for DACK_N
signals for the DMA transfer between a microprocessor’s system memory and the
ISP1160 HC’s internal FIFO buffer RAM.
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the ISP1160
provides an internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H to read, A1H to write) enables the ISP1160’s HC
internal DMA counter for the DMA transfer. When the DMA counter reaches the value
set in the HcTransferCounter register (22H to read, A2H to write), an internal EOT
signal will be generated to terminate the DMA transfer.
Fig 3. Programmed I/O interface between a microprocessor and the ISP1160.
Fig 4. DMA interface between a microprocessor and the ISP1160.
shows the DMA interface between a microprocessor system and the
Rev. 05 — 24 December 2004
PROCESSOR
PROCESSOR
MICRO-
MICRO-
DACK1_N
D [ 15:0 ]
WR_N
RD_N
DREQ1
CS_N
D [ 15:0 ]
IRQ1
WR_N
RD_N
EOT
A1
P bus I/F
P bus I/F
Embedded USB Host Controller
D [ 15:0 ]
WR_N
CS_N
A0
INT
RD_N
RD_N
EOT
D [ 15:0 ]
WR_N
DACK_N
DREQ
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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