ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 97

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 86.
[1]
ISP1161A1_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcDMAConfiguration register: bit allocation
13.1.7 DcDMACounter register (R/W: F3H/F2H)
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
Table 87.
For selecting an endpoint for device DMA transfer, see
This command accesses the DcDMACounter register. The bit allocation is given in
Table
register returns the number of remaining bytes in the current transfer. A bus reset will not
change the programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register
when DMA is re-enabled (DMAEN = 1). See
Bit
15
14
13 to 9
8
7 to 4
3
2
1 to 0
SHORTP
88. Writing to the register sets the number of bytes for a DMA transfer. Reading the
R/W
R/W
0
0
14
6
[1]
[1]
EPDIX[3:0]
DcDMAConfiguration register: bit description
Symbol
CNTREN
SHORTP
-
ODD_EVEN_
IND
EPDIX[3:0]
DMAEN
-
BURSTL[1:0]
reserved
R/W
R/W
0
0
13
5
[1]
[1]
Rev. 05 — 29 September 2009
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter register reaches zero. Bus reset value: unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint), this bit should be
cleared. Bus reset value: unchanged.
reserved
This bit is logic 0 when the last DMA access is a byte (LSB byte
valid; MSB byte invalid). This bit is logic 1 when the last DMA
access is a word (LSB byte valid; MSB byte valid).
Indicates the destination endpoint for DMA, see
Writing a logic 1 enables DMA transfer, a logic 0 forces the end of
an ongoing DMA transfer. Reading this bit indicates whether DMA is
enabled (0 = DMA stopped, 1 = DMA enabled). This bit is cleared
by a bus reset.
reserved
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
reserved
R/W
R/W
0
0
12
4
[1]
[1]
reserved
DMAEN
USB single-chip host and device controller
R/W
R/W
0
11
Section 13.1.6
3
0
[1]
reserved
reserved
Section
R/W
R/W
0
10
2
0
[1]
for more details.
11.2.
ISP1161A1
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
0
0
9
1
[1]
[1]
BURSTL[1:0]
Table
70.
EVEN_IND
ODD_
R/W
97 of 137
0
R
8
0
0
[1]