ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 49

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1161A1_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
10.1.5 HcInterruptEnable register (R/W: 04H/84H)
reserved
R/W
15
7
0
Table 15.
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus when three conditions occur:
Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Bit
31 to 7
6
5
4
3
2
1
0
•
•
•
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
Bit MasterInterruptEnable is set.
RHSC
R/W
14
6
0
HcInterruptStatus register: bit description
Symbol
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
13
5
0
Rev. 05 — 29 September 2009
Description
reserved
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of HcRhPortStatus[1:2] has
changed.
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes value.
UnrecoverableError: This bit is set when the HC detects a system
error not related to USB. The HC does not proceed with any
processing nor signaling before the system error has been corrected.
The HCD clears this bit after the HC has been reset.
OHCI: Always set to logic 0.
ResumeDetected: This bit is set when the HC detects that a device
on the USB is asserting resume signaling from a state of no resume
signaling. This bit is not set when HCD enters the USBResume state.
StartofFrame: At the start of each frame, this bit is set by the HC and
an SOF is generated.
reserved
SchedulingOverrun: This bit is set when the USB schedules for
current frame overruns. A scheduling overrun will also cause the
SchedulingOverrunCount of HcCommandStatus to be incremented.
R/W
UE
12
4
0
reserved
00H
R/W
USB single-chip host and device controller
R/W
RD
11
3
0
R/W
SF
10
2
0
ISP1161A1
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
9
1
0
R/W
49 of 137
SO
8
0
0