ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 68

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 44.
ISP1161A1_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcμPInterruptEnable register: bit allocation
10.4.5 HcμPInterruptEnable register (R/W: 25H/A5H)
reserved
R/W
15
7
0
Table 43.
The bits 6:0 in this register are the same as those in the HcμPInterrupt register. They are
used together with bit 0 of the HcHardwareConfiguration register to enable or disable the
bits in the HcμPInterrupt register.
At power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT1 can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 — read
Code (Hex): A5 — write
Table 45.
Bit
1
0
Bit
15 to 7
6
ClkReady
R/W
14
6
0
HcμPInterrupt register: bit description
HcμPInterruptEnable register: bit description
Symbol
ATLInt
SOFITLInt
Symbol
-
ClkReady
Suspended
Enable
R/W
HC
13
5
0
Rev. 05 — 29 September 2009
Description
0 — no event
1 — implies that the microprocessor must read ATL data from the HC.
This requires that the HcBufferStatus register must first be read. The
time for this interrupt depends on the number of clocks bit set for USB
activities in each ms.
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status, the
HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in
Description
reserved
0 — power-up value
1 — enables Clkready interrupt
Interrupt
Enable
OPR
R/W
12
4
0
reserved
00H
R/W
reserved
USB single-chip host and device controller
R/W
11
3
0
…continued
Interrupt
Enable
EOT
R/W
10
2
0
Section
ISP1161A1
9.5.
Interrupt
Enable
© ST-ERICSSON 2009. All rights reserved.
R/W
ATL
9
1
0
Interrupt
Enable
SOF
R/W
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8
0
0