SCD128410QCE Intel, SCD128410QCE Datasheet - Page 34

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.2.2
5.2.3
5.2.4
34
Warning:
Write Cycles
Write cycle timing and strobe activity is nearly identical to read cycles except that the R/W* signal
must be held low. Write data, strobes, and address inputs must meet setup and hold times as
specified in
accepted the data. Removing both CS* and DS* terminates the cycle.
Service-Acknowledge Cycles
Service-acknowledge cycles are a special-case read cycle. Timing is basically the same as a normal
read cycle, but one of the SVCACK* inputs is activated instead of the CS* input (a slightly longer
setup time is required on the SVCACK* input than on the CS* input). The data that the CD1284
provides during the read cycle is the contents of the Interrupt Vector register associated with the
type of request being acknowledged (RIVR for receive, TIVR for transmit, MIVR for modem, and
PIVR for parallel port) of the channel requesting service (see
As with read and write cycles, DTACK* indicates the end of the cycle. When the CPU removes
DS* and SVCACK* the cycle terminates.
When the CPU has completed the service routine and writes to the EOSRR, a subsequent I/O cycle,
if started immediately, is delayed by approximately 1 s. This is due to the time required by the
internal processor to complete activities associated with the switch out of the service-acknowledge
context. These activities involve FIFO pointer updates and restoration of the environment prior to
the service-request/service-acknowledge procedure. These must be completed before any internal
registers are modified by the CPU.
If the situation occurs that the CPU attempts an access before the internal procedures are complete,
the CD1284 holds off the cycle until it is ready. This does not cause a problem in system designs
that monitor DTACK*; the cycle is extended until DTACK* becomes active and the delay is
automatically met. If a system design does not monitor DTACK*, a mechanism must be provided
to introduce the required delay.
Failure to observe the delay requirement can cause a device malfunction.
DMA Cycles
The CD1284 provides a bidirectional 16-bit DMA interface to the parallel port. This is the only
direct data interface to the port; other 8-bit register accesses use of the normal CPU interface, as
described above.
The handshake between the CD1284 and the DMA circuitry uses two signals: the DMAREQ*
(DMA Request) and the DMAACK* (DMA Acknowledge). The address bus is ignored during
DMA transfers. When internal conditions warrant a DMA transfer (as when the FIFO falls below
the programmed threshold in the forward direction or rises above the threshold in the reverse
direction) and DMA transfers are enabled by the PFCR, the device requests a DMA service by
driving the DMAREQ* signal low. DMAREQ* remains active until the FIFO has less than two
empty locations remaining (forward direction) or until the FIFO has less than 2 bytes remaining
(reverse direction).
In the forward direction, the DMA controller logic responds by placing data on the 16-bit data bus
and driving DMAACK* low. This cycle is repeated until the FIFO has less than two empty
locations remaining or there is no more data to send. In the reverse direction, the CD1284 responds
to the active DMAACK* signal by driving the contents of the DMABUF register onto the data bus.
Chapter
8.0. DTACK* indicates that the cycle is complete and the CD1284 has
Section 5.3.1
for more information).
Datasheet