SCD128410QCE Intel, SCD128410QCE Datasheet - Page 20
SCD128410QCE
Manufacturer Part Number
SCD128410QCE
Description
Manufacturer
Intel
Datasheet
1.SCD128410QCE.pdf
(176 pages)
Specifications of SCD128410QCE
Pin Count
100
Lead Free Status / RoHS Status
Not Compliant
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Part Number:
SCD128410QCE
Manufacturer:
INTEL
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CD1284 — IEEE 1284-Compatible Parallel Interface Controller
20
RESET*
OUTEN
CLK
CLK/2
DB[15:0]
A[6:0]
R/W*
CS*
Symbol
Table 1.
92–99, 2–9
Pin Descriptions (Sheet 1 of 4)
RXD3
TXD2
RXD2
RTS2*
RTS3*
DTR2*
DTR3*
CTS2*
CTS3*
DSR2*
DSR3*
CD2*
CD3*
RI2*
RI3*
N/C
Pin No.
84–90
Pin Name
79
83
73
80
76
78
Type
I/O
O
I
I
I
I
I
I
Type
O
O
O
O
O
–
I
I
I
I
I
I
I
I
I
I
ACTIVE-LOW RESET: This input initializes the device to the default condition. All
internal registers are set to their reset condition and all transfer operations are set to
the default state.
OUTPUT ENABLE: This pin must be ‘1’ to enable output pin functions. When OUTEN
is ‘0’, it forces all output pins to remain in a tristate condition. Typically, OUTEN is used
only for test purposes. User designs must tie this pin to V
SYSTEM CLOCK: This input has a 25-MHz maximum; 16 MHz is the recommended
minimum for satisfactory device performance.
SYSTEM CLOCK DIVIDED BY TWO OUTPUT: This signal is equivalent to the
internal operating clock of the device.
BIDIRECTIONAL DATA BUS: Only DMA transfers and writes to the DMA Buffer
register are true 16-bit operations. During all register writes other than to the DMA
Buffer register, bits [7:0] are written to the addressed register. Register reads duplicate
the register contents on both the lower byte [7:0] and upper byte [15:8].
ADDRESS BUS: Together with CS* or one of the SVCACK* inputs and DS*, this input
selects an On-Chip register for a read or write operation or an acknowledgment to an
service request.
READ/WRITE*: This input must be ‘1’ for a register read operation, and must be ‘0’ for
a register write. R/W* is ignored for DMA operations.
ACTIVE-LOW CHIP SELECT: When active, the input CS* combines with DS*,
initiates an I/O cycle with the CD1284. CS* must be ‘1’ during DMA read/write
operations.
(Sheet 3 of 3)
Number
of Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Number
Pin
17
18
19
26
21
25
20
27
22
28
23
29
24
15
14
74
Reset
State
High
High
High
High
High
Description
CC
through a pull-up resistor.
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