FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 68

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Intel
68
Table 49. IOAPIC Bus Timing
Table 50. SMBus Timing
Table 51. SIU LPC and Serial IRQ Timings
®
82801E C-ICH
NOTES:
t150a
t151a
t152a
t153a
t154a
t155a
t157a
t157b
1. A device will time out when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
Sym
Sym
Sym
t120
t121
t122
t130
t131
t132
t133
t134
t135
t136
t137
t138
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
SIU_LAD[3:0]/SIU_SERIRQ Valid Delay from
SIU_LCLK Rising
SIU_LAD[3:0]/SIU_SERIRQ Output Enable Delay from
SIU_LCLK Rising
SIU_LAD[3:0]/SIU_SERIRQ Float Delay from
SIU_LCLK Rising
SIU_LAD[3:0]/SIU_SERIRQ Setup Time to SIU_LCLK
Rising
SIU_LAD[3:0]/SIU_SERIRQ Hold Time from SIU_LCLK
Rising
SIU_LDRQ# Valid Delay from SIU_LCLK Rising
SIU_LFRAME# Setup Time to SIU_LCLK Rising
SIU_LAD[3:0] Hold Time from SIU_LCLK Rising
APICCD[1:0]# Valid Delay from APICCLK Rising
APICCD[1:0]# Setup Time to APICCLK Rising
APICCD[1:0]# Hold Time from APICCLK Rising
Bus Tree Time Between Stop and Start Condition
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Device Time Out
Cumulative Clock Low Extend Time (slave device)
Cumulative Clock Low Extend Time (master device)
Parameter
Parameter
Parameter
Min
3.0
8.5
3.0
Min
300
250
4.7
4.0
4.7
4.0
Min
25
Advance Information Datasheet
2
2
7
0
2
7
0
Max
12.0
Max
28
11
11
Max
35
25
10
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ms
ms
ms
µs
µs
µs
µs
ns
ns
Notes
Notes
Notes
1
2
3
Fig
10
14
12
10
11
11
11
11
Fig
Fig
10
11
11
24
24
24
24
24
24
25
25