FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 46

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Intel
3.2.17
46
Table 22. Universal Asynchronous Receive And Transmit (UART 0, 1) (Sheet 2 of 2)
Table 23. SIU Interface
®
82801E C-ICH
SIU LPC Interface
SIU_LFRAME#
SIU_LAD[3:0]
SIU_RESET#
SIU_SERIRQ
Signal Name
Signal Name
SIU_LDRQ#
SIU0_RTS#
SIU1_RTS#
SIU_LCLK
SIU0_RXD
SIU1_RXD
SIU0_TXD
SIU1_TXD
SIU0_RI#
SIU1_RI#
Type
I/O
I/O
O
Type
I
I
I
O
O
I
I
SIU LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.
SIU LPC clock input to SIU: 33 MHz LPC clock.
SIU LPC Serial DMA/Master Request Output: Used by SIU devices to indicate a
DMA request.
NOTE: These signals have weak internal pull-up resistors to avoid external glue.
SIU LPC Frame: Indicates the start of an LPC cycle, or an abort.
SIU RESET: This signal should be tied to PCI RESET.
SIU Serial IRQ input: This pin receives the serial interrupt protocol from external
devices. Pull up if unused.
Ring Indicator for UART0 and UART1: Active low, this pin indicates that a
telephone ringing signal has been received by the external agent.
NOTE: These pins are Modem Status Input whose condition can be tested by
Request to Send for UART0 and UART1: When low these pins informs the
modem or data set that 82801E C-ICH UART0 and UART1 are ready to establish
a communication link. The RTS#x(x=0,1) output signals can be set to an active
low by programming the RTSx (x-0,1) (bit1) of the Modem control register to a
logic ‘1’. A Reset operation sets this signal to its inactive state (logic ‘1’). LOOP
mode operation holds this signal in its inactive state.
Serial Inputs for UART0 and UART1: Serial data input from device pin to the
receive port.
Serial Output for UART0 and UART1: Serial data output to the communication
peripheral/modem or data set. Upon reset, the TXD pins will be set to MARKING
condition (logic ‘1’ state).
the processor by reading bit 6 (RI) of the Modem Status register (MSR).
Bit 6 is the complement of the RI# signal. Bit 2 (TERI) of the MSR
indicates whether the DCD# input has changed state since the previous
reading of the MSR. When the RI bit of the MSR changes state an
interrupt is generated if the Modem Status Interrupt is enabled.
Description
Description
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