FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 47

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

3.2.18
3.2.19
Advance Information Datasheet
Table 24. Miscellaneous Signals
Table 25. General Purpose I/O Signals (Sheet 1 of 2)
Miscellaneous Signals
General Purpose I/O
RESERVED1
RESERVED2
GPIO[31:29]
GPIO[28:27]
RTCRST#
SUSCLK
THRM#
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
HL[11]
SPKR
Name
TP0
TP1
TP2
TP3
Name
RI#
Type
—
O
O
Type
I
I
I
I
I
I
I
I
OD
I/O
I/O
I/O
I/O
O
O
No pull-up required. Use a no-stuff or a test point for NAND tree testing.
RTC Reset: When asserted, this signal resets register bits in the RTC well and
sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also
used to enter the test modes documented in “Test Signals” on page 49.
NOTE: Clearing CMOS in an 82801E C-ICH-based platform can be done by
Speaker: The SPKR signal is the output of counter 2 and is internally ANDed with
Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external
speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its
output state is 1.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See
Test Point 0: This signal must have an external pull-up to Vcc3_3.
Thermal Alarm: THRM# is an active low signal generated by external hardware to
start the hardware clock throttling mode. This signal can also generate an SMI# or
an SCI.
Ring Indicate: From the modem interface. This signal can be enabled as a wake
event; this is preserved across power failures.
This signal must have an external pull up to Vcc3_3.
Suspend Clock: This signal is an output of the RTC generator circuit and is used
by other chips for the refresh clock.
Test Point 1: Route to a test point with option to jumper to Vcc1_8. Used for
NAND tree testing. Otherwise jumper to Vcc1_8.
Test Point 2: Route to a test point with option to jumper to V
tree testing. Otherwise jumper to V
Test Point 3: Route to a test point with option to jumper to V
tree testing. Otherwise jumper to V
Not implemented.
Can be input or output. Main power well. Unmuxed.
Not implemented.
Can be input or output. Main power well. Not Muxed.
Can be input or output. Main power well.
Fixed as Output only. Main power well.
Fixed as Output only. Main power well. Open-drain output.
using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low.
“Functional Straps” on page 49for more details.
Description
SS
SS
Description
.
.
Intel
SS
SS
®
. Used for NAND
. Used for NAND
82801E C-ICH
47