FDC37M707-MS Standard Microsystems (SMSC), FDC37M707-MS Datasheet - Page 187

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FDC37M707-MS

Manufacturer Part Number
FDC37M707-MS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37M707-MS

Pin Count
100
Lead Free Status / RoHS Status
Compliant
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been
Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130
NAME
PDATA<7:0>
t1
t2
t3
t4
t5
t6
nAUTOFD
nACK
received. ECP can stall by keeping nAUTOFD low.
ns.
PDATA Valid to nACK Asserted
nAUTOFD Deasserted to PDATA Changed
nACK Asserted to nAUTOFD Deasserted
(Notes 1,2)
nACK Deasserted to nAUTOFD Asserted (Note 2)
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
FIGURE 18 - ECP PARALLEL PORT REVERSE TIMING
DESCRIPTION
t4
t1
t5
187
t3
t6
MIN
80
80
0
0
0
0
t4
TYP
t2
MAX
200
200
UNITS
ns
ns
ns
ns
ns
ns

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