FDC37M707-MS Standard Microsystems (SMSC), FDC37M707-MS Datasheet - Page 151

• Manufacturer Part Number: FDC37M707-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M707-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Pin Multiplex
Controls
Default = 0x02 on
Vcc POR
Force Disk Change
Default = 0x03 on
Vcc POR
Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
UART2 FIFO
Control Shadow
PME Control
Default = 0x00 on
V
TR
POR
NAME
INDEX
(R/W)
(R/W)
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
REG
(R)
Bit[0] Reserved
Bit[1] DMA 3 Select
Bit[2] Reserved
Bit[3] 8042 Select
Bit[4] Reserved
Bit[5:7] Reserved
Bit[0] Force Change 0
Bit[7:1] Reserved
Force Change[0] can be written to 1 but is not
clearable by software.
Force Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND
Force Change 0) OR nDSKCHG
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET
or HARD RESET
nPME signal assertion is disabled (default)
Enables FDC37M70x to assert nPME signal
151
DEFINITION
STATE
C,R
C
C
C