MT45W2MW16BGB-701 IT Micron Technology Inc, MT45W2MW16BGB-701 IT Datasheet - Page 11

• Manufacturer Part Number: MT45W2MW16BGB-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
Power-Up Initialization Timing
In general, the MT45W2MW16BGB devices are high-density alternatives to SRAM and
PSRAM products, popular in low-power, portable applications.
The MT45W2MW16BGB contains a 33,554,432-bit DRAM core organized as 2,097,152
addresses by 16 bits. This device implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous READ protocol.
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their
default settings (see Figure 19 on page 26 and Figure 24 on page 31). V
be applied simultaneously. When they reach a stable level at or above 1.7V, the device
will require 150µs to complete its self-initialization process. During the initialization
period, CE# should remain HIGH. When initialization is complete, the device is ready for
normal operation.
The MT45W2MW16BGB CellularRAM products incorporate a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode, and burst mode READ and WRITE transfers. The
specific interface supported is defined by the value loaded into the bus configuration
register. Page mode is controlled by the refresh configuration register (RCR[7]).
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, and LB#/UB#). READ opera-
tions are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH
(see Figure 5 on page 12). Valid data will be driven out of the I/Os after the specified
access time has elapsed. WRITE operations occur when CE#, WE#, and LB#/UB# are
driven LOW (see Figure 6 on page 12). During asynchronous WRITE operations, the OE#
level is a “Don't Care,” and WE# will override OE#. The data to be written is latched on
the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. Asynchronous opera-
tions (page mode disabled) either can use the ADV input to latch the address, or ADV
can be driven LOW during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT
will be driven while the device is enabled, and its state should be ignored. WE# LOW
time must be limited to
VccQ
Vcc
Vcc = 1.7V
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Device initialization
t PU > 150μs
t
CEM.
11
Device ready for
normal operation
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2007 Micron Technology, Inc. All rights reserved.
CC
and V
CC
Q must