MT45W2MW16BGB-701 IT Micron Technology Inc, MT45W2MW16BGB-701 IT Datasheet

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... DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 WAIT CLK ADV Top view (Ball down) Designator 1.0 specification of –25°C. 2. Contact factory for availability. Part Number Example: MT45W2MW16BGB-701WT ©2007 Micron Technology, Inc. All rights reserved. Features 6 None ...

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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 1: VFBGA Ball Descriptions ...

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... General Description Micron low-power, portable applications. The MT45W2MW16BGB is a 32Mb DRAM core device organized as 2 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases READ/WRITE bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...

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Functional Block Diagram Figure 2: Functional Block Diagram – 2 Meg x 16 A[20:0] CE# WE# OE# Control CLK logic ADV# CRE WAIT LB# UB# Note: Functional block diagrams illustrate simplified device operation. See ball description table, bus operations tables, ...

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Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type H6, G2, H1, D3, A[20:0] Input E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 ADV# Input B5 CE# Input ...

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Bus Operations Table 2: Bus Operations: Asynchronous Mode Mode Power READ Active WRITE Active Standby Standby Idle No operation Configuration Active register WRITE Configuration Active register READ DPD Deep power-down Notes: 1. CLK must be static (HIGH or LOW) during ...

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Table 3: Bus Operations: Burst Mode Mode Power Active Asynchronous READ Active Asynchronous WRITE Standby Standby No operation Idle Active Initial burst READ Initial burst Active WRITE Burst continue Active Active Burst suspend Configuration Active register WRITE Configuration Active register ...

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Part Numbering Information Micron CellularRAM devices are available in several configurations and densities. Figure 3: Part Number Chart Micron Technology Product family 45 = PSRAM/CellularRAM memory Operating core voltage W = 1.7V–1.95V Address locations ...

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... Functional Description In general, the MT45W2MW16BGB devices are high-density alternatives to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W2MW16BGB contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. ...

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Figure 5: READ Operation (ADV = LOW) CE# OE# WE# Address Data LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) CE# OE# WE# Address Data LB#/UB# PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - ...

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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous READ access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. ...

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The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data transferred into (or out of) the memory. WAIT will again be asserted if the burst crosses the ...

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Figure 9: Burst Mode WRITE (4-Word Burst) CLK A[20:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 ...

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Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the ...

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RAM array, and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or ...

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Figure 12: Refresh Collision During WRITE Operation V IH CLK Valid A[20:0] address ADV ...

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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion ...

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Configuration Registers Two user-accessible configuration registers define the device operation. The bus config- uration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh ...

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Figure 14: Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation CLK Latch control register value A[20:0] OPCODE (except A19 A19 t SP CRE ADV CSP 3 ...

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Figure 15: Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation A[20:0] (except A19) Select register 1 A[19] CRE t VPH ADV# CE# OE# WE# LB#/UB# DQ[15:0] Note: A[19] = LOW to read RCR, HIGH to read BCR. PDF: ...

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Figure 16: Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation CLK Latch control register value A[20:0] (except A19 A[19 CRE ADV CSP CE# OE# ...

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Software Access to the Configuration Register Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers ...

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Figure 18: Read Configuration Register Address CE# OE# WE# LB#/UB# Data Note possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or ...

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Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 19 describes the control bits in the BCR. At power-up, the ...

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Table 4: Sequence and Burst Length 4-Word Burst Wrap Starting Burst Address Length BCR[3] Wrap (Decimal) Linear 0 Yes 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 ... 0-1-2-3 1 1-2-3-4 ...

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Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments ...

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Figure 22: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Note: Nondefault BCR setting for WAIT during BURST operation: WAIT active LOW. WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT ...

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Figure 23: Latency Counter (Variable Latency, No Refresh Collision CLK Valid A[20:0] address ADV DQ[15: DQ[15: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm ...

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Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure ...

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Table 6: 32Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Deep Power-Down (RCR[4]) ...

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Table 8: Electrical Characteristics and Operating Conditions Wireless temperature Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Operating Current Asynchronous random READ/ WRITE Asynchronous ...

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... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16BGB device. The typical values shown in Figure 25 are measured with the default on-chip temperature sensor control enabled. Table 9: Partial-Array Refresh Specifications and Conditions ...

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Table 10: Deep Power-Down Specifications Description Deep power-down Table 11: Capacitance Description Input capacitance Input/output capacitance (DQ) Note: These parameters are verified in device characterization and are not 100% tested. Figure 26: AC Input/Output Reference Waveform V CC Input V ...

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Timing Requirements Table 12: Asynchronous READ Cycle Timing Requirements 1 Parameter Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# ...

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Table 13: Burst READ Cycle Timing Requirements 1 Parameter Burst to READ access time CLK to output delay Burst OE# LOW to output delay CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT ...

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Table 14: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW ...

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Table 15: Burst WRITE Cycle Timing Requirements Parameter CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip ...

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Timing Diagrams Figure 29: Asynchronous READ A[20:0] ADV# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...

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Figure 30: Asynchronous READ Using ADV# A[20:0] ADV# LB#/UB# WE# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address VPH ...

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Figure 31: Page Mode READ A[20:4] A[3:0] ADV# LB#/UB# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address Valid address V ...

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Figure 32: Single-Access Burst READ Operation V IH CLK A[20:0] Valid address ADV CSP ...

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Figure 33: 4-Word Burst READ Operation V IH CLK A[20:0] Valid address ADV CSP ...

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Figure 34: READ Burst Suspend V IH CLK Valid A[20:0] V address ADV CSP OE# ...

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Figure 35: Output Delay in Continuous Burst READ with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[20: ADV LB#/UB CE# ...

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Figure 36: CE#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...

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Figure 37: LB#/UB#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...

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Figure 38: WE#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ...

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Figure 39: Asynchronous WRITE Using ADV# A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address AVS t AVH ...

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Figure 40: Burst WRITE Operation V IH CLK A[20:0] Valid address ADV LB#/UB CSP V IH CE# ...

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Figure 41: Output Delay in Continuous Burst WRITE with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[20: ADV LB#/UB CE# ...

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Figure 42: Burst WRITE Followed by Burst READ t CLK V IH CLK A[20:0] Valid V address ADV LB#/UB ...

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Figure 43: Asynchronous WRITE Followed by Burst READ V IH CLK A[20:0] Valid Valid address address AVS t AVH VPH V IH ADV ...

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Figure 44: Asynchronous WRITE Followed by Burst READ with ADV# LOW V IH CLK A[20:0] Valid Valid address address AVS t AVH VPH V IH ADV# ...

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Figure 45: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[20:0] Valid address ADV CSP V IH CE# V ...

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Figure 46: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[20:0] Valid address ADV CSP ...

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Figure 47: Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW V IH A[20:0] Valid address ADV LB#/ ...

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Figure 48: Asynchronous WRITE Followed by Asynchronous READ V IH A[20:0] Valid address AVS t AVH t VPH ADV CVS V IH LB#/UB CE# ...

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... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16BGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...

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Revision History Rev. E, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...