MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 9

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MPC2605 RESPONSE TO 60x TRANSFER ATTRIBUTES
MOTOROLA
NOTES: 1. If a line fill is going to replace a dirty line and the cast out buffer (COB) is full, the line fill will be cancelled. (Unless
TT0 – TT4 TBST
X1X10
X1X10
X1010
X1010
00X10
X0010
X0010
00110
00110
00110
00010
00100
00100
00000
00000
01100
2. If a burst read misses the cache but hits the COB, the MPC2605 will supply the data from the COB, but not
3. If ARTRY is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the to-be-replaced line will
4. If ARTRY is asserted during a read hit, the MPC2605 will abort the process.
5. If a processor burst write occurs right after a snoop write that was a cache hit, the MPC2605 will invalidate the line.
6. If a processor burst write occurs right after a snoop read that was a cache hit, the MPC2605 will update the cache
the line fill is a write that hits in the COB. In this case, the line fill will occur.)
perform a line fill.
recover its old tag (valid, dirty, tag field), and the COB goes back to an invalid condition, even if the line fill is a burst
write to the line in the COB.
If the snoop was a cache miss, the MPC2605 will not perform a write allocate.
and clear the dirty bit. If the snoop was a cache miss, the MPC2605 will perform a write allocate.
X
X
X
X
X
X
0
0
1
1
0
0
0
1
1
1
CI
X
X
X
X
X
1
1
0
0
1
1
1
1
1
0
0
WT
Integrated Secondary Cache for Microprocessors
X
X
X
X
X
1
0
0
0
X
X
X
X
X
X
X
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
Tag Status
Hit Clean
Hit Clean
Hit Clean
Hit Clean
Hit Clean
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
Hit Dirty
Miss
Miss
Hit
Hit
Hit
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Line-fill (processor read miss)
L2 CLAIM, AACK, TA (processor read hit)
Paradox — Invalidate the line (processor n-cacheable read
hit clean line)
Paradox — ARTRY, L2 BR, then write back data, invalidate
the line (processor n-cacheable read hit dirty line)
Line-fill except right after a snoop hit to processor (processor
write miss)
L2 CLAIM, AACK, TA except after a snoop hit to processor
(processor write hit)
Cache update (processor write through WT hit clean)
Cache update, clear dirty bit
Paradox — ARTRY, L2 BR, write back data, keep valid, clear
dirty bit
Paradox — Invalidate the line (processor n-cacheable write
hit clean line)
Paradox — ARTRY, L2 BR, then write back data, invalidate
the line (processor n-cacheable SB write hit dirty line)
Invalidate tag (flush block address-only)
ARTRY, L2 BR, write back data, invalidate tag (flush block
address-only)
No action (clean block address-only)
ARTRY, L2 BR, write back data, reset dirty bit (clean block
address-only)
Invalidate tag (kill block address-only)
MPC2605 Response
MPC2605/D
1, 3, 5, 6
Notes
1, 2, 3
5, 6
4
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