MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 5

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTIONS (continued)
MOTOROLA
11U, 10V – 12V, 14V – 17V,
11B – 17B, 11C, 12C, 10U,
4A – 10A, 4B – 10B, 6C,
11A – 13A, 15A – 18A,
10C, 8U, 9U, 3V – 6V,
16U, 7V, 13V, 2W *
8V, 9V, 3W – 10W*
14A, 18B, 5C, 8C,
Pin Locations
11W – 17W *
19E
19D
18D
2D
2C
1U
3D
3C
1C
3A
1D
2E
1F
2T
2J
1J
2F
DH0 – DH31
DL0 – DL31
CPU2 DBG
CPU3 DBG
CPU4 DBG
DP0 – DP7
Integrated Secondary Cache for Microprocessors
Pin Name
CPU DBG
L2 FLUSH
L2 CLAIM
CPU2 BR
CPU3 BR
CPU4 BR
HRESET
L2 DBG
Freescale Semiconductor, Inc.
L2 BG
L2 BR
L2 CI
DBB
FDN
GBL
For More Information On This Product,
That Implement PowerPC Architecture
Go to: www.freescale.com
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the second CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the third CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the fourth CPU BR.
CPU data bus grant input from arbiter.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the second CPU DBG.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the third CPU DBG.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the fourth CPU DBG.
Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
Data bus busy. Used as input when processor is master, driven as
an output after a qualified L2 DBG when MPC2605 is the bus
master. Note: To operate in Fast L2 mode, this pin must be tied high.
Data bus parity input and output.
Flush done I/O used for communication between other MPC2605
devices. Must be tied together between all MPC2605 parts along
with a pullup resistor.
Global transaction. Always negated when MPC2604 is bus master.
Hard reset input from processor bus. This is an asynchronous input
that must be low for at least 16 clock cycles to ensure the MPC2605
is properly reset.
Bus grant input from arbiter.
Bus request I/O. Normally used as an output.
Secondary cache inhibit sampled, after assertion of TS. Assertion
prevents linefill.
L2 cache claim output. Used to claim the bus for processor initiated
memory operations that hit the L2 cache. L2 CLAIM goes true (low)
before the rising edge of CLK following TS true. Because this output
is not always driven, a pullup resistor may be necessary to ensure
proper system functioning.
Data bus grant input. Comes from system arbiter, used to start data
tenure for bus operations where MPC2605 is the bus master.
Causes cache to write back dirty lines and clears all tag valid bits.
Description
MPC2605/D
5