MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 18

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
READ HIT/WRITE HIT
MPC2605 asserts L2 CLAIM the cycle after TS to
inform the memory controller that there is a cache hit
and the cache will control the rest of the transaction.
L2 CLAIM is held through the cycle after AACK is
asserted. Since there are no active data tenures from
previous transactions, the MPC2605 asserts AACK
18
Figure 1 shows a read hit from an idle bus state. The
DH0 – DH31,
DL0 – DL31
CPU DBG
L2 CLAIM
A0 – A31
CPU BG
AACK
TBST
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High-Z
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
Figure 1. Burst Read (or Write) Hit
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1
A
A1
2
the cycle after TS is asserted. Note that there must be a
qualified assertion of CPU DBG in the same cycle as
the assertion of TS for the MPC2605 to respond with
TA in the next cycle. CPU DBG does not affect the
timing of L2 CLAIM or AACK.
difference is the processor drives the data instead of
the MPC2605.
The write hit timing is virtually the same. The only
A2
3
A3
4
A4
5
6
MOTOROLA