MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 13

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

the cycle after AACK is asserted. This cycle is
referred to as the ARTRY window, since it is the cycle
that all devices sample ARTRY to determine if the
address tenure has been successfully completed.
ARTRY, then the next bus master is free to assert TS
the cycle after the ARTRY window to start a new
address tenure. If ARTRY is asserted in the ARTRY
window, all devices that are not asserting ARTRY
must negate their bus request in the following cycle.
This next cycle is called the BR window. The purpose
of this protocol is to give immediate bus mastership to
the device that asserted ARTRY with the expectation
that the device will take this opportunity to clean up
whatever circumstances caused it to assert ARTRY.
Typically, this involves writing data back to memory
to maintain coherence in the system.
Data Tenures
address tenures. They require two conditions to start:
an assertion of TS that initiates a data transaction and a
qualified assertion of the bus master's data bus grant.
For a data bus grant to be considered qualified, no
device on the bus may be asserting DBB in the cycle
that the data bus grant is asserted.
transactions and burst transactions. The type is
determined by the state of TBST during the address
tenure of the transaction. If the bus master asserts
TBST, the transaction is a burst transaction and will
require four assertions of TA in order to complete
normally. If TBST is negated during the address
tenure, the transaction only requires one assertion of
TA, thus the name single-beat.
transaction depends on whether the transaction is a
read or a write. For a read transaction, the slave device
drives the data bus. For a write transaction, the master
drives the data bus. In all data transactions, the slave
device asserts TA to indicate that either valid data is
present on the bus, in the case of a read; or that it is
reading data off the data bus, in the case of a write.
The master device asserts DBB the cycle after it has
been granted the data bus and keeps it asserted until
the data tenure has completed.
The address tenure for the transaction can be aborted
by an assertion of ARTRY. Or, the slave device may
MOTOROLA
If an address tenure is not aborted by an assertion of
Data tenures are more complicated to define than
Data transactions come in two types: single-beat
The device that drives the data bus during a data
A data tenure can be aborted in two different ways.
Integrated Secondary Cache for Microprocessors
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assert TEA to indicate that some error condition has
been detected. Either event will prematurely terminate
the data tenure.
Data Streaming
wait state between the completion of one data tenure
and the start of the next. This turnaround cycle avoids
the contention on the data bus that would occur if one
device starts driving data before another device has
had a chance to turn off its data bus drivers. When a
cache read hit is pipelined on top of another cache read
hit, there is no need for this turnaround cycle since the
same device will be driving the data bus for both data
tenures. The 60x bus has the ability to remove this
unnecessary wait state and allow back-to-back cache
read hits to stream together. This ability is only
enabled if the system is put into Fast L2 mode. Note
that not all processors implementing the PowerPC
architecuture support Fast L2 mode.
data streaming capability is that the system arbiter
must be sophisticated enough to identify situations
where streaming may occur. on recognizing these
situations, it must assert the processor's data bus grant
in the cycle coincident with the fourth assertion of TA
of the first cache read, so that the data tenure for the
second cache read may commence in the next cycle.
CPU DBG, the MPC2605 must not be aware of the
processor’s assertions of DBB. This means that the
DBB pin of the MPC2605 must be tied to a pullup
resistor rather than connected to the system DBB. This
forces the system arbiter to a level of sophistication
such that it only supplies qualified data bus grants and
thus, the DBB signal is unnecessary to the whole
system.
device acts as an independent cache. Zero wait state
data streaming can only occur if the back-to-back read
hits occur in a given device. If the second read hit is
not in the device as the first read hit, a wait state will
occur between the two data tenures (2-1-1-1-2-1-1-1
timing).
Data Bus Parking
processor read or write hit starting in the cycle after
the processor has asserted TS. This is referred to as a
For the majority of data transactions there must be a
One of the requirements for taking advantage of this
Because it only recognizes qualified assertions of
Note: In a multi-chip configuration each MPC2605
The MPC2605 has the ability to respond to a
MPC2605/D
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