MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 11

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

SYSTEM USAGE AND REQUIREMENTS
cache. A look-aside cache is defined as a cache that
resides on the same bus as the processor, memory
controller, DMA bridge, and arbiter. The advantage of
a look-aside cache is that when the processor makes a
memory request, the cache adds no delay to the
memory controller's response time in the event that the
request cannot be satisfied by the cache. However,
there are certain system requirements that must be met
before a look-aside cache can be used.
Comprehension of L2 CLAIM
request that is issued by the processor, there must be a
mechanism for the cache to inform the memory
controller that it has detected a cache hit and will
satisfy the processor's request. The MPC2605 has a
signal called L2 CLAIM that is asserted whenever a
cache hit is detected. Any memory controller with
which the MPC2605 is to be used must have the
ability to monitor this signal.
Pipeline Depth
that a new transaction can be initiated before a
previous transaction has fully completed. The level of
pipelining that exists on the bus is defined by how
many new data transactions have been initiated while
the original transaction is still being processed. By this
definition, the MPC2605 can only work in a one level
deep pipeline. In the presence of transactions for
which it has asserted L2 CLAIM, the MPC2605 can
control the level of pipelining by delaying its assertion
of AACK. However, for transactions that it cannot
control, the MPC2605 is dependent on the memory
controller to control pipeline depth. Thus, another
system requirement for the use of the MPC2605 is the
use of a memory controller that only allows one level
deep of pipelining on the 60x bus.
Bus Mastering
that seek to use the MPC2605 as a copy-back cache, as
opposed to a write-through cache. The requirement is
that the system arbiter must have the ability to allow
MOTOROLA
The MPC2605 is a high-performance look-aside
Because the memory controller sees every memory
The 60x bus allows pipelining of transactions such
Bus mastering is a requirement only for systems
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
FUNCTIONAL OPERATION
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the MPC2605 to become a bus master. Specifically,
the system arbiter must be able to recognize assertions
of L2 BR and must have the ability to assert L2 BG
and L2 DBG.
what should already exist. All other necessary control
signals are signals that are required for the processor
to communicate with the memory controller, DMA
bridge, and arbiter.
CONFIGURATION PINS
CFG1, CFG2, CFG3, and CFG4.
CFG0 – CFG2
implement the different cache sizes supported by the
MPC2605.
CFG3
DMA bridge and memory controller are resident in the
same device. In such systems there is internal
communication between these two functional units.
Bus transactions generated by the DMA bridge are
solely for the purpose of keeping the system coherent.
They are not explicit requests from memory that have
data tenures associated with them. However, some
chipsets are designed with the memory controller and
DMA bridge partitioned into different devices. In
These are the only requirements above and beyond
The MPC2605 has five configuration pins: CFG0,
These three configuration pins are used to
256KB: For a single chip implementation, CFG0,
512KB: This two-chip configuration requires both
1MB:
Many core logic chipsets are designed such that the
CFG1, and CFG2 should all be tied low.
parts to have CFG0 tied low and CFG1
tied high. CFG2 is used as a chip select
when it matches the value of A26.
Therefore, one device must have CFG2
tied low and the other device must have
CFG2 tied high.
The four-chip configuration requires all
four devices to have CFG0 tied high. The
CFG1, CFG2 vector becomes the chip
select when it matches the A25, A26
vector. Therefore, each of the four parts
must have a unique value of the CFG[1:2]
vector.
MPC2605/D
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