RD38F2240WWZDQ1 Micron Technology Inc, RD38F2240WWZDQ1 Datasheet - Page 45

• Manufacturer Part Number: RD38F2240WWZDQ1
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWZDQ1

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Table 21: PASR Address Pattern for PSRAM
9.4
9.4.1
9.4.2
November 2007
Order Number: 311760-10
16 Mbit
Device
0
0
0
0
1
1
1
1
A2
PSRAM Access to Control Register
The PSRAM control registers (BCR and RCR) can be updated at any time to select
desired operating modes.
The control registers can be accessed by the hardware access method using the CRE
pin or software access method consisting of a series of reads and writes.
The two methods are described in the sections below.
PSRAM Hardware Control Register Access
Hardware write or read access to the PSRAM registers occurs by applying the SCR and
FCR commands with the CRE signal asserted high. During the SCR and FCR commands,
A[19:18] designates target register. A[19:18] = 00b accesses the Refresh Control
Register (RCR), A[19:18] = 10b accesses the Bus Control Register (BCR). The SCR and
FCR commands can be applied in either synchronous or asynchronous mode.
After applying the SCR command in asynchronous mode, CE# must be pulled high for
minimum of tCPH prior to initiating any subsequent command. After applying the SCR
command in synchronous mode, CE# must be pulled high for minimum of tCPBH prior
to initiating a subsequent synchronous command. Additionally, when applying the
synchronous SCR command CE# must remain low to complete a burst of one write
even though the DQ values are ignored by the PSRAM. To insure predictable device
behavior, an SCR command should not be terminated or interrupted prematurely and
ADV# should not go low more than one time prior to CE# being pulled high.
PSRAM Software Register Access
Software access of the registers uses a sequence of asynchronous read and
asynchronous write operations. First 2 asynchronous reads to the maximum address
are performed followed by an asynchronous write to the maximum address. The data
values during this asynchronous write select the appropriate register. During the fourth
operation DQ[15:0] transfer data in to or out of the bits [15:0] of the registers.
During the software access sequence, it is necessary to:
• Toggle CE# between every read or write command (so the Device can distinguish 4
• Maintain the address input until it is latched by ADV# or until CE# goes high. After
separate cycles).
setting the control registers using the software access method, CE# must be pulled
high for minimum of tCPH prior to initiating any subsequent command.
0
0
1
1
0
0
1
1
A1
0
1
0
1
0
1
0
1
A0
16
8
4
2
0
8
4
2
Density (Mb)
Full Die
1/2 of die
1/4 of die
1/8 of die
None
1/2 of die
1/4 of die
1/8 of die
Active Section
00000h – FFFFFh
00000h – 7FFFFh
00000h – 3FFFFh
00000h – 1FFFFh
0
80000h – FFFFFh
C0000h – FFFFFh
E0000h – FFFFFh
Address
Datasheet
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