RD38F2240WWZDQ1 Micron Technology Inc, RD38F2240WWZDQ1 Datasheet - Page 42

• Manufacturer Part Number: RD38F2240WWZDQ1
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWZDQ1

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 18: PSRAM Burst Length Sequences
9.3.2
Datasheet
42
Note:
Burst Length
Continuous
16
32
4
8
EOR = End of Row
Fixed Length Burst with Wrap Off will increment the address until a row boundary
crossing is reached. Fixed Length Bursts will continue to wrap around and cycle through
their limited address space until terminated or interrupted. The burst length setting is
used for both Write and Read operations.
PSRAM Refresh Control Register
The Refresh Control Register (RCR) allows for additional stand-by power savings by
making use of the Partial-Array Self Refresh (PASR) and Deep Power Down (DPD)
features. The RCR is programmed via the Control Register Set command (with CRE = 1
and A[18:19] = 00b) and retains the stored information until it is reprogrammed or the
device loses power.
Reserved bit fields of the RCR should be ignored during a Fetch Control Register
command as they may have undefined values even when set to 0b with a Set Control
Register command. The RCR contents can only be set or changed when the PSRAM is in
idle state.
00000b
00001b
...
11110b
11111b
00000b
00001b
...
11110b
11111b
00000b
00001b
...
11110b
11111b
00000b
00001b
...
11110b
11111b
00000b
00001b
...
11110b
11111b
Starting Address
[A4:A0]
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
Wrap Off
Burst Address Sequence (decimal)
128-Mbit W18 Family with Synchronous PSRAM
0-1-2-3-0-1-2-3-...
1-2-3-0-1-2-3-1-...
...
30-31-28-29-30-31-28-29-...
31-28-29-30-31-28-29-30-...
0-1-2-3-4-5-6-7-0-1-2-3-...
1-2-3-4-5-6-7-0-1-2-3-4-...
...
30-31-24-25-26-27-28-29-30-...
31-24-25-26-27-28-29-30-31...
0-1-2-...-13-14-15-0-1-2-...
1-2-3-...-14-15-0-1-2-3-...
...
30-31-16-17-...-29-30-31-16-17-...
31-16-17-...-29-30-31-16-17-...
0-1-2-...-29-30-31-0-1-2-...
1-2-3-...-29-30-31-0-1-2-...
...
30-31-0-...-29-30-31-0-1-...
31-0-1-...-29-30-31-0-1-...
0-1-2-3-4-5-6-7-...-EOR
1-2-3-4-5-6-7-8-...-EOR
...
30-31-32-33-34-...-EOR
31-32-33-34-35-...-EOR
Wrap On
Order Number: 311760-10
November 2007