XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 221
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XC3S500E-4FT256I
Manufacturer Part Number
XC3S500E-4FT256I
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4FT256I
Package
256FTBGA
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
190
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4FT256I
Manufacturer:
XILINX
Quantity:
1 400
Company:
Part Number:
XC3S500E-4FT256I
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
Table 152: FG400 Package Pinout (Continued)
User I/Os by Bank
Table 153
distributed between the four I/O banks on the FG400 pack-
age.
Table 153: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
indicates how the 304 available user-I/O pins are
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
R
I/O Bank
XC3S1200E
XC3S1600E
Pin Name
0
1
2
3
Maximum
304
I/O
78
74
78
74
FG400
M14
Ball
D11
H12
U10
H11
H13
E17
L17
J10
N9
H9
K4
J7
J8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Type
JTAG
156
I/O
43
35
30
48
www.xilinx.com
Table 152: FG400 Package Pinout (Continued)
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
INPUT
Bank
20
12
18
12
62
All Possible I/O Pins by Type
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
DUAL
XC3S1200E
XC3S1600E
21
24
46
Pin Name
1
0
VREF
24
6
6
6
6
Pinout Descriptions
(1)
FG400
Ball
M11
M13
N10
N12
K11
J12
L10
L12
M9
N8
K9
CLK
0
0
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
16
8
8
(2)
(2)
Type
(1)
221