XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 145

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 105: Switching Characteristics for the DLL (Continued)
Notes:
1.
2.
3.
4.
DS312-3 (v3.8) August 26, 2009
Product Specification
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Lock Time
LOCK_DLL
Delay Lines
DCM_DELAY_STEP
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum
jitter of "±[1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
Symbol
(3)
R
(4)
Phase offset between the CLKIN and CLKFB inputs
Phase offset between DLL outputs
When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition at
its LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase
Finest delay resolution
Description
www.xilinx.com
CLK0 to CLK2X
(not CLK2X180)
All others
5 MHz < F
F
CLKIN
15 MHz
> 15 MHz
CLKIN
<
Table 77
Device
All
All
All
and
Table
DC and Switching Characteristics
Min
20
-
-
-
-
-
104.
-5
±[1% of
±[1% of
CLKIN
CLKIN
period
+ 100]
period
+ 200]
±200
Max
Speed Grade
600
40
5
Min
20
-
-
-
-
-
-4
±[1% of
±[1% of
CLKIN
period
+ 100]
CLKIN
period
+ 200]
±200
Max
600
40
5
Units
ms
ps
ps
ps
μs
ps
145