XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 16
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XC3S500E-4FT256I
Manufacturer Part Number
XC3S500E-4FT256I
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4FT256I
Package
256FTBGA
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
190
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4FT256I
Manufacturer:
XILINX
Quantity:
1 400
Company:
Part Number:
XC3S500E-4FT256I
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
Functional Description
Table 6: Single-Ended IOSTANDARD Bank Compatibility
16
OCLK1
OCLK2
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I_18
HSTL_III_18
IOSTANDARD
Single-Ended
PAD
D1
D2
From
Fabric
OCLK1
OCLK2
d
D1
D2
d+1
d
d+2
Figure 10: Output DDR
d+1
d+3
Output
Input/
1.2V
d+2
-
-
-
-
-
-
-
-
-
d+4
d+3
d+5
D
D
d+4
Output
Input/
Input
1.5V
V
Q
d+6
Q
CCO
-
-
-
-
-
-
-
-
d+5
d+7
Supply/Compatibility
d+6
Output
Output
Output
d+8
DS312-2_23_030105
Input/
Input/
Input/
Input
Input
1.8V
d+7
-
-
-
-
-
PAD
d+9
www.xilinx.com
d+10
d+8
Output
Input/
Input
Input
Input
Input
Input
2.5V
-
-
-
-
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards
Table
differential pairs to support any of the differential signaling
standards
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the Xilinx Software Manuals and
Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
particular V
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
7). The majority of the I/Os also can be used to form
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
3.3V
(Table
CCO
voltage,
7).
Table 6
N/R
N/R
V
N/R
N/R
N/R
N/R
N/R
N/R
0.9
1.1
REF
Input Requirements
DS312-2 (v3.8) August 26, 2009
(1)
(1)
and
Table 7
Product Specification
Voltage (V
Termination
Board
list all of the
(Table 6
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
1.8
TT
and
)
R