HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 357

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Figure 46.
Figure 47.
5.20.5.3
July 2009
Order Number: 318378-005US
SMBus Configuration Read (Word Writes/Word Reads, PEC Enabled)
Figure 47, “SMBus Configuration Read (Write Bytes/Read Bytes, PEC Enabled)”
byte reads.
SMBus Configuration Read (Write Bytes/Read Bytes, PEC Enabled)
Configuration Register Write Protocol
Configuration writes are accomplished through a series of SMBus writes. As with
configuration reads, a write sequence is first used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (block, word or byte).
Examples of configuration writes are illustrated in
Write (Block Write, PEC Enabled)”
(Write Bytes, PEC Enabled).”
to the System Management Bus (SMBus) Specification, Version 2.0. For diagram
compactness, “Register Number” is also sometimes referred to as “Reg Number” or
“Register”.
Sr
Sr
Sr
S
S
S
S
S
Sr
Sr
Sr
Sr
Sr
S
S
S
S
S
S
S
S
S
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
®
5100 MCH Chipset
W A
W A
W A
W A
W A
R A
R A
R A
W A
W A
W A
W A
W A
W A
W A
W A
W A
R A
R A
R A
R A
R A
Cmd = 10010001
Cmd = 01010001
Cmd = 10010001
Cmd = 00010001
Cmd = 01010000
Data[23:16]
Data[7:0]
Status
Cmd = 10010000
Cmd = 00010000
Cmd = 00010000
Cmd = 01010000
Cmd = 10010000
Cmd = 00010000
Cmd = 00010000
Cmd = 00010000
Cmd = 01010000
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
Status
For the definition of the diagram conventions below, refer
A
A
A
A
A
A
A
A
Register Number[15:8]
through
Bus Number
Data[31:24]
Data[15:8]
PEC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Device/Function
Register[15:8]
Register[7:0]
Bus Number
Figure 50, “SMBus Configuration Write
A
N P
A
A
A
PEC
PEC
PEC
PEC
PEC
Register Number[7:0]
Device/Function
Figure 48, “SMBus Configuration
PEC
PEC
Intel
N P
N P
N P
N P
N P
A
A
A
A
®
5100 Memory Controller Hub Chipset
A
N P
N P
A
PEC
PEC
PEC
PEC
PEC
PEC
A P
A P
A P
CLOCK STRETCH
A P
CLOCK STRETCH
Datasheet
uses
A P
A P
357