HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 264

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

4.3
4.3.1
4.3.2
4.3.3
Intel
Datasheet
264
®
5100 Memory Controller Hub Chipset
System Memory Area
The low/medium memory regions range from 1 MB to 4 GB. It consists of sub-regions
for Firmware, Processor memory mapped functions, and the Intel
specific registers.
The Extended Memory Area covers from 10 0000h (1 MB) to FFFF FFFFh (4 GB-1)
address range and it is divided into the following regions:
Main System DRAM Address Range (0010 0000h to Top of System Memory)
The address range from 1 MB to the top of system memory is mapped to system
memory address range controlled by the MCH. The Top of Low/Medium Memory (TOLM)
is limited to 4 GB of DRAM. All accesses to addresses within this range will be
forwarded by the MCH to the system memory.
The MCH provides a maximum system memory address decode space of 4 GB. The
MCH does not remap APIC memory space. The MCH does not limit system memory
address space in hardware.
System Memory
See
15 MB - 16 MB Window (ISA Hole)
The Intel
F0 0000h - FF FFFFh. All transactions to this address range are treated as system
memory.
Extended SMRAM Space (TSEG)
SMM space allows system management software to partition a region in main memory
to be used by system management software. This region is protected for access by
software other than system management software. When the SMM range is enabled,
memory in this range is not exposed to the Operating System. The Intel
Chipset allows accesses to this range only when the SMMEM# signal on the processor
bus is asserted with the request. If SMMEM# is deasserted, accesses to the SMM Range
are master aborted. If SMMEM# is asserted the access is routed to main memory. The
Intel
to route the access.
Extended SMRAM Space is different than the SMM space defined within the VGA
address space, A 0000h - B FFFFh. This region is controlled by the Intel
Chipset registers SC.EXSMRC.TSEG_SZ and SC.EXSMRTOP.ESMMTOP. The TSEG SMM
space starts at ESMMTOP - TSEG_SZ and ends at ESMMTOP. This region may be 512
kB, 1 MB, 2 MB, or 4 MB in size, depending on the TSEG_SZ field. ESMMTOP is
relocatable to accommodate software that wishes to configure the TSEG SMM space
before MMIO space is known. The ESMMTOP will default to the same default value as
Top Of Low Memory (TOLM), defined by the TOLM register.
• Main System Memory from 1 MB to the Top of Memory; 4 GB system memory.
• PCI Memory space from the Top of Memory to 4 GB with two specific ranges:
• APIC Configuration Space from FEC0 0000h (4 GB–20 MB) to FEC8 FFFFh and FEE0
• High BIOS or Firmware area is the last 16 MB before the 4 GB boundary
0000h to FEEF FFFFh
Section 4.3.9, “Main Memory Region.”
®
5100 MCH Chipset uses the SMM enable and range registers to determine where
®
5100 MCH Chipset does not support the legacy ISA hole between addresses
Intel
®
5100 MCH Chipset—System Address Map
Order Number: 318378-005US
®
5100 MCH Chipset
®
®
5100 MCH
5100 MCH
July 2009