HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 34

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Note:
Table 3.
Table 4.
Intel
Datasheet
34
®
5100 Memory Controller Hub Chipset
SSTL_2
CMOS
Host Interface signals that perform multiple transfers per clock cycle may be marked as
either “4x” (for signals that are “quad-pumped”) or 2x (for signals that are “double-
pumped”).
Processor address and data bus signals are logically inverted signals. In other words,
the actual values are inverted of what appears on the processor bus. This must be
taken into account and the addresses and data bus signals must be inverted inside the
MCH host bridge. All processor control signals follow normal convention. A 0 indicates
an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an
active level (high voltage) if the signal has no # suffix.
Signal Naming Conventions
Table 4, “Buffer Signal Types”
Buffer Signal Types
RR{0/1/2}XX
RR[2:0]
RR{0/1/2}
RR{P/N}
RR# or RR[2:0]#
I
O
A
I/O
Buffer Direction
Convention
Expands to: RR0XX, RR1XX, and RR2XX. This denotes similar signals on replicated buses.
Expands to: RR[2], RR[1], and RR[0]. This denotes a bus.
Expands to: RR2, RR1, and RR0. This denotes electrical duplicates.
Expands to: RRP, RRN. This denotes inverted electrical duplicates.
Denotes an active low signal or bus.
Input signal
Output signal
Analog
Bidirectional (input/output) signal
Stub Series Terminated Logic 2.6 V compatible signals
CMOS buffers
lists the reference terminology used for signal types.
Description
Expands to
Intel
®
5100 MCH Chipset—Signal Description
Order Number: 318378-005US
July 2009