HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 303

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.9
July 2009
Order Number: 318378-005US
ISRs should record all events in the status registers that they process and clear all
events detected. There should be no lingering status upon ISR exit. It is the software’s
responsibility to handle MSIs.
If an ISR does not follow the requirement to read the Interrupt Control register
(INTRCTRL), and the ISR is called twice back-to-back such that it reads Attention
Status register (ATTNSTATUS) both times, a second MSI could overwrite the first one
and hang the system.
Legacy/8259 Interrupts
8259 interrupt controller is supported in Intel
request is delivered using the interrupt group sideband signals LINT[1:0] (aka., NMI/
INTR) or through an I/O xAPIC using the message-based interrupt delivery mechanism
with the delivery mode set to ExtINT (111b). There can be only one active 8259
controller in the system.
The mechanism in which a PCI Express* device requests an 8259 interrupt is a PCI
Express* inband message. (Assert_INTA/B/C/D, Deassert_INTA/B/C/D).
The target processor for the interrupt uses the interrupt acknowledge transaction to
obtain the interrupt vector from the 8259 controller. The Intel
forwards the interrupt acknowledge to the ICH9R where the active 8259 controller
resides.
The Intel
interrupts (for example, during boot). 8259 interrupts from PCI Express* devices will
be sent in-band to the Intel
the ICH9R.
The Intel
from each PCI Express* and assert virtual interrupt signals to the 8259 through the
inband “Assert_(Deassert)_INTx” messages. This is done by a tracking bit per interrupt
(A, B, C, D) in each PCI Express* which are combined (OR’d) into virtual signals that
are sent to the ICH9R. Each interrupt signal (A, B, C, D) from each PCI Express* is
OR’ed together to form virtual INT A, B, C, and D signals to the ICH9R
(Assert_(Deassert)_INTA/B/C/D (assertion encoding)). When all of the tracking bits for
a given interrupt (A, B, C, or D) are cleared from all PCI Express* ports, the virtual
signal A, B, C, or D is deasserted via the inband Deassert_INTx message.
For PCI Express* hierarchies, interrupts will be consolidated at each level. For example,
a PCI Express* switch connected to a Intel
only send a maximum of four interrupts at a time, regardless of how many interrupts
are issued downstream.
SMI (System Management Interrupt) interrupts are initiated by the SMI# signal in the
platform. On accepting a System Management Interrupt, the processor saves the
current state and enters SMM mode.
Note that the Intel
LINT[1:0] and SMI signals. They are present on the ICH9R and the processor. The
Intel
Interrupts”
interrupts can be generated by routing the Intel
to the appropriate ICH9R pin.
®
5100 MCH Chipset interrupt signals described in
®
®
®
5100 MCH Chipset will support PCI Express* devices that generate 8259
5100 MCH Chipset will have a mechanism to track inband 8259 interrupts
can be routed to the ICH9R to generate an SMI interrupt. Similarly SCI
5100 MCH Chipset
®
5100 MCH Chipset core components do not interact with the
®
5100 MCH Chipset which will forward these interrupts to
®
5100 MCH Chipset PCI Express* port will
®
5100 MCH Chipsets. 8259 interrupt
®
5100 MCH Chipset interrupt signals
Intel
Section 5.7, “Chipset Generated
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset
Datasheet
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