HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 142

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
142
®
5100 Memory Controller Hub Chipset
Device:
Function:
Offset:
14:12
Bit
15
11
10
9
8
RWST
Attr
RW
RW
RO
RO
RV
7-2, 0
0
74h
Default
000
0h
1
0
0
0
Reserved.
MRRS: Max_Read_Request_Size
This field sets maximum Read Request size generated by the Intel
MCH Chipset. The PCI Express* port must not generate read requests with
size exceeding the set value.
000: 128 bytes max read request size
001: 256 bytes max read request size
010: 512 bytes max read request size
011: 1024 bytes max read request size
100: 2048 bytes max read request size
101: 4096 bytes max read request size
110: Reserved
111: Reserved
The MCH will not generate read requests larger than 64 bytes in general on
the outbound side due to the internal microarchitecture (CPU initiated, DMA
or Peer-to-peer). Hence the field is set to 000b encoding.
ENNOSNP: Enable No Snoop
When set, the PCI Express* port is permitted to set the “No Snoop bit” in the
Requester Attributes of transactions it initiates that do not require hardware
enforced cache coherency. Typically the “No Snoop bit” is set by an
originating PCI Express* device down in the hierarchy.
The Intel
received TLP even if ENNOSNP is enabled. For outbound traffic, the Intel
5100 MCH Chipset does not need to snoop.
APPME: Auxiliary Power Management Enable
1: Enables the PCI Express* port to draw AUX power independent of PME
AUX power.
0: Disables the PCI Express* port to draw AUX power independent of PME
AUX power.
Devices that require AUX power-on legacy operating systems should continue
to indicate PME AUX power requirements. AUX power is allocated as
requested in the AUX_Current field on the Power Management Capabilities
Register (PMC), independent of the PMEEN bit in the Power Management
Control & Status Register (PMCSR) defined in
- Power Management Control and Status Register.”
PFEN: Phantom Functions Enable
This bit enables the PCI Express* port to use unclaimed functions as
Phantom Functions for extending the number of outstanding transaction
identifiers. The Intel
complex) and is hardwired to 0
ETFEN: Extended Tag Field Enable
This bit enables the PCI Express* port to use an 8-bit Tag field as a requester.
The Intel
hardwired to 0.
®
®
5100 MCH Chipset never sets or modifies the “No snoop bit” in the
5100 MCH Chipset does not use this field (Root complex) and is
®
5100 MCH Chipset does not implement this bit (Root
Intel
®
Description
5100 MCH Chipset—Register Description
Section 3.8.9.2, “PMCSR[7:2,0]
Order Number: 318378-005US
®
July 2009
5100
®